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| ISDN Remote Power Controller (IRPC) PSB 2120 CMOS IC Features q Switched mode DC/DC-converter q Switched mode DC/DC-converter q CCITT (I.430) ISDN compatible q Integrated 200 V power FET (only PSB 2120-P in P-DIP-22) q Low power dissipation q Supply voltage range 10 V to 60 V q Input undervoltage detection q Programmable overcurrent protection q Soft start q Control circuit to achieve minimum start-up current q Power housekeeping input q Oscillator synchronization input/output q Polarity reversal detection q High voltage CMOS-technology 60 V P-DSO-24-1 P-DIP-22 Type PSB 2120-P PSB 2120-T Version V B5 V B5 Ordering Code Q67100-H8645 Q67100-H6278 Package P-DIP-22 P-DSO-24-1 (SMD) The PSB 2120 is a Pulse Width Modulator (PWM) circuit designed for fixed-frequency switching regulators especially for telephony and ISDN-environments. The PSB 2120 is fully compatible with the CCITT-power recommendations on the "S"-interface. Coupled with a few external components it can provide a stable 5 V DC-supply for subscriber terminals (TE's) or network terminators (NT's). It can also be programmed for higher output voltages, e.g. to supply the S-lines with 40 V. In telephony and ISDN-systems a high conversion yield is crucial to maintain functionality in all supply conditions via "S"- or "U"-interfaces. The PSB 2120 design and technology realizes high conversion efficiency and low power dissipation. It should be recognized that the PSB 2120 can also be used in numerous DC/DC-conversion systems other than ISDN-power supplies. Semiconductor Group 3 12.92 PSB 2120 Pin Configurations (top view) P-DSO-24 P-DIP-22 Semiconductor Group 2 PSB 2120 Pin Definitions and Functions Pin Pin No. No. P-DSO P-DIP 1 1 Symbol Input (I) Output (O) I/O Definition Function SYNC Synchronization Input for synchronization of the oscillator to an external frequency, or output to synchronize multiple devices. The external timing components of the ramp generator are attached to this pin. Error amplifier output and Pulse Width Modulator (PWM) input for loop stabilization network. Non-inverting input of the error amplifier. 2 2 RC I RC-Oscillator 3 3 COMP O Compensation 4 5 6 7 8 11 N.C. N.C. 14 4 5 6 7 8 9 10 11 12 VP VN CSS EME POL GA DR SO I I I O I O O O I Positive Voltage Sense Negative Voltage Inverting input of the error amplifier. Sense Soft Start Capacitor Emergency Polarity Detection Gate Drain Source Input Capacitor The capacitor at this pin determines the soft-start characteristic. A low input voltage at POL will activate the output EME. POL is the input to a non inverting Schmitt-trigger. Output of the FET-driver. Drain connection of the power FET. Source connection of the power FET. CIN CIN has to be connected to the input buffer-capacitor and a current limiting charging-resistor. Semiconductor Group 3 PSB 2120 Pin Definitions and Functions (cont'd) Pin Pin No. No. P-DSO P-DIP 15 16 17 18 19 20 13 14 15 16 17 18 Symbol Input (I) Output (O) I O I I I I/O Definition Function ENA CO CN CP GND Enable Comparator output Comparator neg. input Comparator pos. input Ground External supply A high input voltage at this pin will stop the IRPC-function. Connections of the universal usable comparator. All analog and digital signals are referred to this pin. Output of the internal CMOS-supply. Via VEXT the internal CMOS-circuits can be supplied from an external DC-supply in order to reduce chip power dissipation. When the voltage difference between these two pins exceeds 100 mV, the digital current limiting becomes active. Output of the 4.0 V reference voltage. VEXT 21 22 23 24 19 20 21 22 IN IP VREF VS I I O I Negative current sense Positive current sense Reference voltage Supply voltage VBAT is the positive input voltage. Semiconductor Group 4 PSB 2120 Figure 1 IRPC Functional Diagram Semiconductor Group 5 PSB 2120 Functional Description The reference provides a 4.0 V voltage for the regulation loop. A high gain error amplifier compares the reference voltage with the switch mode supply output voltage. The output of the error amplifier is compared with a periodic linear ramp, which is generated by the sawtooth-oscillator circuit. The comparator output is a fixed-frequency, variable pulse width logic signal, which passes through logic circuits to the high voltage power-switching-FET. A digital current limiting device suppresses the PWM logic signal when the voltage difference at the current limit sense input reaches 100 mV. In this case the control logic inhibits double pulses during one oscillator period. Start-Up Procedure Before the switched-mode DC/DC-converter starts, a sequence of several conditions has to be passed in order to avoid any system malfunction. The primary undervoltage detection inhibits the converter function. This insures that all control functions have stabilized in the proper state when the turn on voltage (ca. 10 V) is reached, and it prevents start-up glitches. In case of connecting the TE to powered lines or if a line is powered up, the charge current of the primary buffer capacitor is limited by an external resistor (figure 2). This resistor is short-circuited by the PSB 2120 when the voltage drop across it falls below approximately 2.0 V. The residual resistance of this short-circuit is about 3 . In case of a primary undervoltage detection the short-circuit will be always deactivated. So, the DC/DC-converter does not start until the charging of the primary buffer capacitor is completed, and the maximum line input voltage is reached. If this feature is not desired, CIN has to be connected to GND. In this case the primary current measuring circuit turns off, to reduce chip-power dissipation from 9 mW to 6 mW. In order to avoid high current peaks during the charging of the secondary capacitors or line capacitors in case of supplying an S-interface, a soft start circuit is implemented in the PSB 2120. This circuit requires an external capacitor, connected between CSS and GND. In addition, the enable input (ENA) allows an external switch-on/switch-off control. If the DC/DCconverter is disabled via ENA, the soft-start-capacitor at pin CSS is discharged. This input can also be used for several other functions, e.g. secondary overvoltage protection. Semiconductor Group 6 PSB 2120 Figure 2 DC/DC-Conversion The PSB 2120 contains a SIPMOS-transistor for power handling. Non-isolated and isolated SMPSconfigurations are possible. Logic and analog circuits are implemented in CMOS in order to achieve low power dissipation. The error amplifier compares the sensed voltage with a reference attached to VP and thus controls the Pulse Width Modulator (PWM). The conversion frequency is generated by a sawtooth oscillator which can be controlled by external RC-components (figure 4) or by an external synchronization signal. The PSB 2120 is synchronized by the rising edge of the sync signal, whose frequency must be 10 % higher than the free run frequency, determined by the RC-components. The SYNC-pin can also be used as a trigger-output. As long as the capacitor of the sawtooth oscillator is discharged, SYNC is high. The output of the PWM is processed by the control logic and fed to the SIPMOS-transistor. The control logic suppresses higher oscillations of the regulation loop caused e.g. in case of current limit detection. Semiconductor Group 7 PSB 2120 Polarity Detection Emergency conditions are signaled to the TE by the reversed polarity of the line feeding voltage. When polarity reversal is detected via pin POL of the PSB 2120, emergency conditions are signaled to the microprocessor via pin EME, which should shut down all activity except simple telephony functions to minimize power dissipation. The polarity detection circuit can also be used for other detection or protection-functions, e.g. programmable primary undervoltage detection. Power Housekeeping An integrated 6 V linear voltage regulator supplies the internal circuits during the start-up phase. Power dissipation of this regulator can be reduced, if an auxiliary winding of the transformer or an external supply is used for that purpose by connecting it to VEXT. If the input voltage at VEXT reaches 6.2 V the internal linear voltage regulator turns off and the internal circuits are fed from this external voltage. In this case the input current at VEXT is approx. 0.5 mA. Note: An internal 7.5 V Zener-diode protects the VEXT input against overvoltages. The maximum Zener-current is 2 mA! If the external supply isn't stabilized, the input current must be limited (e.g. by a resistor)! Interface to Microprocessor The PSB 2120 offers two TTL-compatible signals: EME and CO. The EME (Emergency-output) becomes active, if polarity reversal is detected. CO is the output of a universal usable comparator; e.g.: to generate a microprocessor-reset signal. Semiconductor Group 8 PSB 2120 PSB 2120 Applications in ISDN-Environments Figure 3 shows an example out of the wide application field of the PSB 2120. In the network termination one PSB 2120 supplies the internal IC's directly from the U-interface. A second IRPC, also powered from the U-line, supplies the S-interface if the main supply of the NT is out of order. A third IRPC is used in the main supply to regulate the S-line feeding voltage. In the subscriber terminal the PSB 2120 is used for feeding the internal circuits. The PSB 2120 accommodates both galvanically isolated and non-isolated configuration. Considering the diversity of DC/DC-converter applications, this part of the specification only shows how to use the special ISDN-features of the PSB 2120. The switching frequency of the SMPS is programmable by two external components. Figure 4 shows the switching frequency as a function of RT and CT. The minimum configuration so as to be able to use the PSB 2120 in ISDN-applications is by using a flyback converter (figure 5). The time constant of the soft start circuit is programmed by a capacitor at Pin CSS. Figure 6 shows the primary start-up current limitation by connecting Pin CIN. To reduce chip-powerdissipation, an auxiliary winding of the transformer is used to switch off the internal linear CMOSsupply (pin VEXT). Polarity reversal is detected by pin POL. Figure 7 shows the realization of a microprocessor-reset-signal with the universal usable comparator of the IRPC. Figure 8 shows the PSB 2120 in flyback configuration with transformer isolation. Figure 9 shows the PSB 2120 in flyback configuration with opto isolation, which is useful for a high reliability galvanically isolated application. Semiconductor Group 9 PSB 2120 Figure 3 IRPC in ISDN-Concept Semiconductor Group 10 PSB 2120 Switching Frequency Figure 4 Switching Frequency as a Function of RT and CT Semiconductor Group 11 PSB 2120 Figure 5 PSB 2120 Minimum Configuration Semiconductor Group 12 PSB 2120 Figure 6 Advanced IRPC-Application with Power Housekeeping and Polarity Reversal Detection Semiconductor Group 13 PSB 2120 According to the application in figure 5 and an output power of 500 mW, t1 will be 400 ms and t2 50 ms. Figure 7 Generation of a P-Reset Signal with the PSB 2120 Semiconductor Group 14 PSB 2120 Figure 8 PSB 2120 in Flyback Configuration with Transformer Isolation Semiconductor Group 15 PSB 2120 Figure 9 PSB 2120 in Flyback Configuration with Opto Isolation Semiconductor Group 16 PSB 2120 Absolute Maximum Ratings (All pin references made for P-DIP-22) Parameter Supply voltage DR (pin 10) referred to S0 (pin 11) Continuous drain current (pin 10) Supply voltage VBAT (pin 22) referred to GND Analog/digital input voltage referred to GND (pins 2, 3, 4, 5, 7, 8, 13, 15, 16, 19, 20) Reference output current (pin 21) Symbol Limit Values 200 350 60 6 -5 2 -5 -5 -5 - 25 to 85 - 40 to 125 50 Unit V mA V V mA mA mA mA mA C C K/W VS IDR VBAT VI A/D IO REF II Z IO IO SYNC IO DR TA Tstg Tj VEXT input Z-current VEXT output current SYNC-output current (pin 1) Driver output current (pin 9) Ambient temperature under bias Storage temperature Thermal resistance junction - ambient MOS-Handling: The integrated SIPMOS-transistor (pin 9, 10 and 11) has to be protected against electrostatic charges. The input gate-source (pin 9 and pin 11) must be protected against 10 V. DC Characteristics TA = 0 to 70 C, VS = 11 to 60 V Parameter Symbol min. Reference VREF Limit Values typ. max. Unit Test Condition TA = 25 C Output voltage Line regulation Load regulation Temperature stability Load current VREF O VREF Line VREF Load VREF TS IREF Load 3.92 4.0 4.08 60 V mV mV mV IL = 0 mA, VS = 40 V VS = 20 to 60 V, IL = 0 mA, IL = 0.1 to 0.3 mA, VS = 40 V 20 25 40 0.5 mA Semiconductor Group 17 PSB 2120 DC Characteristics (cont'd) Parameter Symbol min. Limit Values typ. max. Unit Test Condition Oscillator SYNC (pin1), RC (pin 2) fOSC = 20 kHz, RT 39 k 1 %, CT= 1 nF 1 %, TA = 25 C Initial accuracy Voltage stability of fOSC Temperature stability of fOSC Max. frequency H-sawtooth voltage L-sawtooth voltage H-sync output level L-sync output level 10 1 5 3 % % % kHz 3.4 2.0 5.25 0.8 V V V V fmax VH VL VOH VOL 180 3.0 1.6 2.4 250 3.2 1.8 3.5 0.2 RT = 27 k CT = 39 pF IL = 0.5 mA VS EXT 6.3 V IL = 20 A Error Amplifier COMP (pin 3), VP (pin 4), VN (pin 5) Input offset voltage Input current Common mode range DC open loop gain Common mode rejection Unit gain bandwidth Supply voltage rejection H-output voltage L-output voltage VIO II VC GVO kCMR f VOH VOL 1.8 60 60 0.5 60 4 3 0 70 70 1 70 5.5 0.02 10 25 4.0 mV nA V dB dB MHz dB V V VCM = 3.0 V VOFFSET = 15 mV CL (pin) 10 pF IL = 100 A IL = 10 A Current Limit Comparator IP (pin 20), IN (pin 19) TA = 25 C Sense voltage Input current Input voltage range Response time to signal at GA (pin 9) VSense II VI tRes 85 0 100 0 1 115 100 1 2 mV nA V s VS = 40 V IN = 0 V IP = 0 200 mV Semiconductor Group 18 PSB 2120 DC Characteristics (cont'd) Parameter Symbol min. Pulse Width Modulator Duty cycle Undervoltage Detection Start-up threshold Threshold hysteresis Soft Start CSS (pin 6) Charging current Limit Values typ. max. Unit Test Condition td 0 50 % VUV St VUV Hy 8.1 10 0.3 11 V V IC 2 4 8 A Output Driver GA (pin 9) TA = 25 C, CL = CGS - Power FET H-output voltage H-output voltage L-output voltage Rise time Fall time Output current External Supply VEXT (pin 18) Output voltage Output current Input voltage Z-current Enable Input ENA (pin 13) H-input voltage L-input voltage Response time to signal at GA (pin 9) H-input current VOH VOH VOL tr tf IO 4.5 V ISource = 5 mA ISource = 0 mA ISink = 5 mA V EXT = 6.3 V V EXT = 6.3 V V EXT 0.3 130 70 0.4 200 200 5 V V ns ns mA VO IO VI IZ 6.0 5.8 2 7.5 2 V mA V mA VIH VIL tRes IIH 2.0 0.5 0.2 2.5 5.25 0.8 1 20 V V s A TA = 25 C Semiconductor Group 19 PSB 2120 DC Characteristics (cont'd) Parameter Symbol min. Comparator CN (pin 15), CP (pin 16), TA = 25 C Input offset voltage Input bias current Input voltage range Response time to signal at CO (pin 14) Limit Values typ. max. Unit Test Condition VIO II VI tRes 1.8 3 0 0.2 10 25 4.5 1 mV nA V s VCM = 3 V Short Circuit GI (pin 12), TA = 25 C Sense voltage VSense RDS (on) 1 2 3 3 4 V (VS - VCIN) Polarity Detection POL (pin 8), EME (pin 7) H-input voltage L-input voltage H-input current Response time to signal at EME (pin 7) VIH VIL IIH tRes 2.0 0.1 1 0.2 5.25 0.8 10 1 V V A s Digital Outputs EME (pin 7), CO (pin 14) IOUT = 0.5 mA H-output voltage L-input voltage VOH VIL 2.4 3.5 0.2 5.25 0.4 V V V EXT 6.3 V Power FET GA (pin 9), DR (pin 10), SO (pin 11) RDS (on) ton toff Leakage current Power consumption 4 55 110 9 6 150 200 200 10 ns ns nA mA ID = 300 mA td (on) td (off) ILeak Ptot VDS = 110 V VS = 40 V fOSC = 20 kHz V EXT = 6.3 - 6.7 V CGS 200 pF Semiconductor Group 20 |
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